The present invention relates to a multilayer wiring board in which a plurality of resin insulation layers and conduction layers are alternately laminated on each other and a manufacturing method thereof.
A semiconductor integrated circuit chip (hereinafter referred to as “IC chip”) has various applications such as a microprocessor for a computer. In recent years, there has been a tendency to provide an increasing number of terminals on the IC chip with a smaller terminal pitch for higher operation speed and performance of the IC chip. These plurality of terminals are generally arranged close to each other in an array on a bottom side of the IC chip and are connected by flip-chip bonding to terminals of a motherboard. However, the direct mounting of the IC chip on the motherboard is difficult due to a great difference between the terminal pitch of the IC chip and the terminal pitch of the motherboard. It is thus common practice to produce a semiconductor package by mounting the IC chip on a chip mounting wiring board, and then, mount the semiconductor package on the motherboard.
As the chip mounting wiring board of the semiconductor package, there has been put into practical use a multilayer wiring board in which a plurality of build-up layers are formed on top and bottom sides of a core substrate. The multilayer wiring board utilizes as the core substrate, for example, a resin substrate formed of resin-impregnated glass fiber material (e.g. glass/epoxy resin) and made much larger in thickness than the build-up layers so as to attain high rigidity and function as a reinforcement. Further, electrical wiring (e.g. through-hole conductors) is formed through the core substrate for electrical connection between the build-up layers on the top and bottom sides of the core substrate.
For high-speed operation of the IC chip, high-frequency signals have recently been applied to the IC chip. In this case, the mounting of the IC chip on the build-up wiring board results in a transmission loss of the high-frequency signal or a circuit malfunction of the IC chip and becomes a cause of interference with the high-speed operation of the IC chip as the electrical wiring produces a high inductance in the core substrate. As a solution to such a problem, Japanese Laid-Open Patent Publication No. 2009-117703 (abbreviated as “JP 2009-117703A”) proposes a coreless multilayer wiring board that has no core substrate of relatively large thickness so as to shorten the total wiring length of the multilayer wiring board and reduce the transmission loss of high-frequency signals for high-speed operation of the IC chip.
In JP 2009-117703A, the build-up layers are provided with alternating resin insulation layers and conduction layers. The resin insulation layers, including not only an outer resin insulation layer as the outermost build-up layer but also inner resin insulation layers as the inner build-up layers, are formed of the same resin material, whereas the conduction layers are formed by e.g. plating on the resin insulation layers. In this type of multilayer wiring board, a silica filler is commonly added to the resin insulation layers in order to improve the adhesion of the resin insulation layers to the conduction layers and to decrease the thermal expansion coefficient of the resin insulation layers. Further, connection terminals are formed in the outer resin insulation layer and connected by flip-chip bonding via solder bumps to the IC chip; and an underfill material of liquid curable resin is filled in a clearance between the outer resin insulation layer and the IC chip in order to improve the thermal fatigue life of the solder bumps.